forked from github/verilator
45 lines
1.1 KiB
Systemverilog
45 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: public clock signal
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2022 by Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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`ifdef VERILATOR
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// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
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`define IMPURE_ONE ($c(1))
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`else
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// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
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`define IMPURE_ONE (|($random | $random))
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`endif
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module t (
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input clk,
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input dummy_clk // Never toggled from C++
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);
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int count;
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logic [7:0] pub_byte /* verilator public_flat_rw */ = 123;
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logic [7:0] comb_byte;
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always_comb comb_byte = `IMPURE_ONE ? pub_byte : '0;
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always_ff @(posedge clk) begin
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count <= count + 1;
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if (comb_byte != pub_byte) begin
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$display("%%Error: comb_byte (%0d) != pub_byte (%0d)", comb_byte, pub_byte);
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$stop;
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end
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if (count == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge dummy_clk) begin
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// verilator lint_off MULTIDRIVEN
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comb_byte = ~pub_byte;
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// verilator lint_on MULTIDRIVEN
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end
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endmodule
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