forked from github/verilator
d6c2e2faf6
This will still warn if a case item is completely covered by previous
items, but will no longer complain about overlaps like this:
priority casez (foo_i)
2'b ?1: bar_o = 3'd0;
2'b 1?: bar_o = 3'd1;
Before, there was a warning for the second statement because the first
two patterns match 2'b11.
51 lines
1.5 KiB
Systemverilog
51 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Rupert Swarbrick.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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value
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);
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input [1:0] value;
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sub u_sub(.value(value), .out0(), .out1());
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endmodule
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module sub (input logic [1:0] value,
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output logic [2:0] out0,
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output logic [2:0] out1);
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always_comb begin
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// This case statement shouldn't cause any warnings. Although the cases overlap (2'b11 matches
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// both 2'b?1 and 2'b1?), the second item matches 2'b10 and the first one doesn't.
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priority casez (value)
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2'b ?1: out0 = 3'd0;
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2'b 1?: out0 = 3'd1;
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default: out0 = 3'd2;
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endcase
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// This case statement *should* cause a warning: the second case is completely covered by the
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// first.
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priority casez (value)
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2'b ?1: out1 = 3'd0;
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2'b ?1: out1 = 3'd1;
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default: out1 = 3'd2;
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endcase
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// This case statement should cause a warning too: the second case and third cases are
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// completely covered by the first. But it should only cause one: like with overlapping cases,
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// we assume that the author messed up the first case, so there's no real benefit to reporting
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// each thing it subsumes.
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priority casez (value)
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2'b ?1: out1 = 3'd0;
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2'b ?1: out1 = 3'd1;
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2'b 11: out1 = 3'd2;
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default: out1 = 3'd3;
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endcase
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end
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endmodule
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