forked from github/verilator
21 lines
528 B
Systemverilog
21 lines
528 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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`define UDALL
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`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif
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`undefineall
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`ifdef UDALL `error "undefineall failed" `endif
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`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif
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initial begin
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$finish;
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end
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endmodule
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