forked from github/verilator
75 lines
1.9 KiB
Systemverilog
75 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`undefineall
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// Definitions as speced
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// Note there are trailing spaces, which spec doesn't show properly
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`define D(x,y) initial $display("start", x , y, "end");
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'`D( "msg1" , "msg2" )'
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'initial $display("start", "msg1" , "msg2" , "end");'
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'`D( " msg1", )'
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'initial $display("start", " msg1" , , "end");'
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'`D(, "msg2 ")'
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'initial $display("start", , "msg2 ", "end");'
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'`D(,)'
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'initial $display("start", , , "end");'
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'`D( , )'
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'initial $display("start", , , "end");'
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//`D("msg1") // ILLEGAL: only one argument
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//`D() // ILLEGAL: only one empty argument
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//`D(,,) // ILLEGAL: more actual than formal arguments
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// Defaults:
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`define MACRO1(a=5,b="B",c) $display(a,,b,,c);
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'`MACRO1 ( , 2, 3 )'
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'$display(5,,2,,3);'
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'`MACRO1 ( 1 , , 3 )'
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'$display(1 ,,"B",,3 );'
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'`MACRO1 ( , 2, )'
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'$display(5,,2,,);'
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//`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c
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`define MACRO2(a=5, b, c="C") $display(a,,b,,c);
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'`MACRO2 (1, , 3)'
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'$display(5,,,,"C");'
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'`MACRO2 (, 2, )'
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'$display(5,,2,,"C");'
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'`MACRO2 (, 2)'
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'$display(5,,2,,"C");'
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`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c);
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'`MACRO3 ( 1 )'
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'$display(1 ,,0,,"C");'
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'`MACRO3 ( )'
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'$display(5,,0,,"C");'
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//`MACRO3 // ILLEGAL: parentheses required
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`define DTOP(a,b) a + b
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'`DTOP( `DTOP(b,1), `DTOP(42,a) )'
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'b + 1 + 42 + a'
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// Local tests
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`define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c'
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`MACROQUOTE();
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'"==)" "((((" () ';
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// Also check our line counting doesn't go bad
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`define MACROPAREN(a=(6),
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b=(eq=al),
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c) 'a b c'
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`MACROPAREN(
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,,
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ZOT)
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HERE-`__LINE__ - Line71
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//======================================================================
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