forked from github/verilator
29 lines
829 B
Systemverilog
29 lines
829 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_param_first_a (/*AUTOARG*/
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// Outputs
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varwidth, par
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);
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parameter X = 1;
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parameter FIVE = 0; // Overridden
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parameter TWO = 2;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [4:0] par; // From b of t_param_first_b.v
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output [X:0] varwidth; // From b of t_param_first_b.v
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// End of automatics
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t_param_first_b #(X,FIVE,TWO) b
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(/*AUTOINST*/
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// Outputs
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.par (par[4:0]),
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.varwidth (varwidth[X:0]));
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endmodule
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