forked from github/verilator
40 lines
940 B
Systemverilog
40 lines
940 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug1578
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module t;
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parameter N = 4;
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typedef logic array_t[N];
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parameter array_t MASK = mask_array();
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//TODO bug1578: parameter MASK = mask_array();
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function array_t mask_array();
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for(int i = 0; i < N; i++) begin
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mask_array[i] = i[0];
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end
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endfunction
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array_t norm;
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initial begin
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if (N != 4) $stop;
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norm = mask_array();
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if (norm[0] != 1'b0) $stop;
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if (norm[1] != 1'b1) $stop;
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if (norm[2] != 1'b0) $stop;
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if (norm[3] != 1'b1) $stop;
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if (MASK[0] != 1'b0) $stop;
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if (MASK[1] != 1'b1) $stop;
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if (MASK[2] != 1'b0) $stop;
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if (MASK[3] != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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