forked from github/verilator
26 lines
575 B
Systemverilog
26 lines
575 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef struct {
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string a, b;
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struct {
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bit a, b;
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} has;
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} strings;
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endpackage
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module t (/*AUTOARG*/);
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initial begin
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pkg::strings stct;
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stct.a = "hello";
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stct.b = "world";
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$display("%s, %s (%1b, %1b)", stct.a, stct.b, stct.has.a, stct.has.b);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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