forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
77 lines
1.6 KiB
Plaintext
77 lines
1.6 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Fri Jun 22 19:27:45 2018
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$end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 / clk $end
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$scope module t $end
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$var wire 32 % c1_count [31:0] $end
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$var wire 1 # c1_start $end
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$var wire 32 ( c3_count [31:0] $end
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$var wire 1 ' c3_start $end
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$var wire 1 / clk $end
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$var wire 8 $ cyc [7:0] $end
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$var wire 32 & s2_count [31:0] $end
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$var wire 1 # s2_start $end
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$scope module c1 $end
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$var wire 32 % count [31:0] $end
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$var wire 32 * runner [31:0] $end
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$var wire 32 ) runnerm1 [31:0] $end
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$var wire 1 # start $end
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$upscope $end
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$scope module c3 $end
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$var wire 32 ( count [31:0] $end
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$var wire 32 . runner [31:0] $end
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$var wire 32 - runnerm1 [31:0] $end
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$var wire 1 ' start $end
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$upscope $end
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$scope module s2 $end
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$var wire 32 & count [31:0] $end
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$var wire 32 , runner [31:0] $end
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$var wire 32 + runnerm1 [31:0] $end
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$var wire 1 # start $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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