forked from github/verilator
c207e98306
What previously used to be per module static constants created in V3Table and V3Prelim are now merged globally within the whole model and emitted as part of a separate constant pool. Members of the constant pool are global variables which are declared lazily when used (similar to loose methods).
46 lines
931 B
Systemverilog
46 lines
931 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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enum {
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CASE_0 = 0,
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CASE_1 = 1,
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CASE_2 = 2,
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CASE_4 = 4,
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CASE_5 = 5,
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DEFAULT = 99
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} e;
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reg [2:0] cyc;
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initial cyc = 0;
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always @(posedge clk) cyc <= cyc + 1;
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always @* begin
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case (cyc)
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3'b000: e = CASE_0;
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3'b001: e = CASE_1;
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3'b010: e = CASE_2;
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3'b100: e = CASE_4;
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3'b101: e = CASE_5;
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default: e = DEFAULT;
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endcase
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end
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always @(posedge clk) begin
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$display("cyle %d = %d", cyc, e);
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if (cyc == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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