forked from github/verilator
45 lines
997 B
Systemverilog
45 lines
997 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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test,
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// Inputs
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clk
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);
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input clk;
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output reg [5:0] test;
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parameter STATE1 = 6'b000001;
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parameter STATE2 = 6'b000010;
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parameter STATE3 = 6'b000100;
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parameter STATE4 = 6'b001000;
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parameter STATE5 = 6'b010000;
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parameter STATE6 = 6'b100000;
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always @(posedge clk) begin
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$display("Clocked");
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case (test)
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STATE1: test <= STATE2;
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STATE2: test <= STATE3;
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STATE3: test <= STATE4;
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STATE4: test <= STATE5;
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STATE5: test <= STATE6;
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default: test <= STATE1;
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endcase
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end
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int cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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