forked from github/verilator
51 lines
891 B
Systemverilog
51 lines
891 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define MAX 10
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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int cyc = 0;
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logic [`MAX:0] val = {`MAX+1{1'b0}};
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initial val[0] = 1;
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Test1 t1(clk, cyc, val);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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$display("val = %20b", val);
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if (cyc < `MAX) begin
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val[cyc] <= 0;
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val[cyc+1] <= 1;
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end else begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test1 (
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clk,
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cyc,
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val
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);
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input clk;
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input [`MAX:0] val;
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input integer cyc;
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assert property(@(posedge clk) not (&val));
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assert property(@(posedge clk) (not ~|val));
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endmodule
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