forked from github/verilator
44 lines
844 B
Systemverilog
44 lines
844 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This test verifies that a top-module can be specified which
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// is instantiated beneath another module in the compiled source
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// code, even when that top-module has a module both above and beside
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// it in the hierarchy.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Dan Petrisko.
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// SPDX-License-Identifier: CC0-1.0
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module top(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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always_ff @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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under under();
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endmodule
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module under(/*AUTOARG*/
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);
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endmodule
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module faketop(/*AUTOARG*/
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);
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under under();
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top top();
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// Stop immediately if this module is instantiated
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initial begin
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$stop();
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end
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endmodule
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