forked from github/verilator
113 lines
3.1 KiB
Systemverilog
113 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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interface intf ();
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integer value;
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endinterface
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module fanout
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#(parameter int N = 1)
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(
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intf upstream,
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intf downstream[N-1:0]
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);
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genvar i;
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for (i = 0; i < N; i = i + 1)
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assign downstream[i].value = upstream.value;
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endmodule
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module xbar
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(
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input logic clk,
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input int cyc,
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intf Masters[1:0]
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);
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localparam NUM_DEMUX_OUT = 2 * 4;
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localparam NUM_MUX_IN = 2 * 4;
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intf demuxOut[NUM_DEMUX_OUT-1:0]();
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intf muxIn[NUM_MUX_IN-1:0]();
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//fan out master connections to the crossbar matrix
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fanout #(.N(4)) fanout_inst0
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(.upstream(Masters[0]),
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.downstream(demuxOut[3:0]));
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fanout #(.N(4)) fanout_inst1
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(.upstream(Masters[1]),
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.downstream(demuxOut[7:4]));
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//the crossbar matrix assignments, done as 1D arrays because verilator doesn't currently support >1D arrays of interfaces
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genvar slv, mst;
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for (slv = 0; slv < 4; slv = slv + 1) begin
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for (mst = 0; mst < 2; mst = mst + 1) begin
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localparam int muxIdx = (slv*2)+mst;
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localparam int demuxIdx = slv+(mst*4);
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assign muxIn[muxIdx].value = demuxOut[demuxIdx].value;
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end
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end
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always @(posedge clk) begin
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if (cyc == 5) begin
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`checkh(Masters[0].value, 2);
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`checkh(Masters[1].value, 1);
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// The first 4 demuxOut values should have the value of the first Master
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`checkh(demuxOut[0].value, Masters[0].value);
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`checkh(demuxOut[1].value, Masters[0].value);
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`checkh(demuxOut[2].value, Masters[0].value);
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`checkh(demuxOut[3].value, Masters[0].value);
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// The next 4 demuxOut values should have the value of the second Master
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`checkh(demuxOut[4].value, Masters[1].value);
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`checkh(demuxOut[5].value, Masters[1].value);
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`checkh(demuxOut[6].value, Masters[1].value);
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`checkh(demuxOut[7].value, Masters[1].value);
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// Each 2 mux inputs should have one input from each master, in order from low to high
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`checkh(muxIn[0].value, Masters[0].value);
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`checkh(muxIn[1].value, Masters[1].value);
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`checkh(muxIn[2].value, Masters[0].value);
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`checkh(muxIn[3].value, Masters[1].value);
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`checkh(muxIn[4].value, Masters[0].value);
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`checkh(muxIn[5].value, Masters[1].value);
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`checkh(muxIn[6].value, Masters[0].value);
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`checkh(muxIn[7].value, Masters[1].value);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t
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(
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clk
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);
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input clk;
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intf masters[1:0]();
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int cyc;
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xbar sub
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(.clk,
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.cyc,
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.Masters(masters));
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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masters[0].value <= 2;
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masters[1].value <= 1;
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end
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end
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endmodule
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