forked from github/verilator
66 lines
1.4 KiB
Systemverilog
66 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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parameter N = 4;
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// verilator lint_off LITENDIAN
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interface a_if #(parameter PARAM = 0) ();
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logic long_name;
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modport source (output long_name);
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modport sink (input long_name);
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endinterface
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module intf_source
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(
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input logic [0:N-1] intf_input,
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a_if.source i_intf_source[0:N-1]
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);
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generate
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for (genvar i=0; i < N;i++) begin
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assign i_intf_source[i].long_name = intf_input[i];
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end
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endgenerate
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endmodule
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module intf_sink
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(
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output [0:N-1] a_out,
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a_if.sink i_intf_sink[0:N-1]
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);
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generate
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for (genvar i=0; i < N;i++) begin
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assign a_out[i] = i_intf_sink[i].long_name;
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end
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endgenerate
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endmodule
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module t
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(
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clk
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);
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input clk;
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logic [0:N-1] a_in;
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logic [0:N-1] a_out;
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logic [0:N-1] ack_out;
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a_if #(.PARAM(1)) tl_intf [0:N-1] ();
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intf_source source(a_in, tl_intf);
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intf_sink sink(a_out, tl_intf);
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initial a_in = '0;
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always @(posedge clk) begin
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a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
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ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
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if (ack_out != a_out) begin
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$stop;
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end
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if (& a_in) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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