forked from github/verilator
104 lines
2.6 KiB
Systemverilog
104 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc = 0;
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reg [63:0] crc;
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reg [31:0] sum;
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wire [15:0] out0;
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wire [15:0] out1;
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wire [15:0] inData = crc[15:0];
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wire wr0a = crc[16];
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wire wr0b = crc[17];
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wire wr1a = crc[18];
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wire wr1b = crc[19];
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fifo fifo (
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// Outputs
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.out0 (out0[15:0]),
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.out1 (out1[15:0]),
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// Inputs
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.clk (clk),
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.wr0a (wr0a),
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.wr0b (wr0b),
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.wr1a (wr1a),
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.wr1b (wr1b),
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.inData (inData[15:0]));
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 32'h0;
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end
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else if (cyc>10 && cyc<90) begin
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sum <= {sum[30:0],sum[31]} ^ {out1, out0};
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end
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else if (cyc==99) begin
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if (sum !== 32'he8bbd130) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module fifo (/*AUTOARG*/
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// Outputs
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out0, out1,
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// Inputs
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clk, wr0a, wr0b, wr1a, wr1b, inData
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);
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input clk;
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input wr0a;
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input wr0b;
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input wr1a;
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input wr1b;
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input [15:0] inData;
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output [15:0] out0;
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output [15:0] out1;
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reg [15:0] mem [1:0];
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reg [15:0] memtemp2 [1:0];
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reg [15:0] memtemp3 [1:0];
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assign out0 = {mem[0] ^ memtemp2[0]};
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assign out1 = {mem[1] ^ memtemp3[1]};
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always @(posedge clk) begin
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// These mem assignments must be done in order after processing
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if (wr0a) begin
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memtemp2[0] <= inData;
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mem[0] <= inData;
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end
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if (wr0b) begin
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memtemp3[0] <= inData;
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mem[0] <= ~inData;
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end
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if (wr1a) begin
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memtemp3[1] <= inData;
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mem[1] <= inData;
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end
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if (wr1b) begin
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memtemp2[1] <= inData;
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mem[1] <= ~inData;
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end
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end
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endmodule
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