forked from github/verilator
207 lines
6.2 KiB
Systemverilog
207 lines
6.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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by_width #(1) w1 (.clk(clk));
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by_width #(31) w31 (.clk(clk));
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by_width #(32) w32 (.clk(clk));
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by_width #(33) w33 (.clk(clk));
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by_width #(63) w63 (.clk(clk));
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by_width #(64) w64 (.clk(clk));
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by_width #(65) w65 (.clk(clk));
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by_width #(95) w95 (.clk(clk));
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by_width #(96) w96 (.clk(clk));
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by_width #(97) w97 (.clk(clk));
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reg signed [15:0] a;
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reg signed [4:0] b;
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reg signed [15:0] sr,srs,sl,sls;
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reg [15:0] b_s;
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reg [15:0] b_us;
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task check_s(input signed [7:0] i, input [7:0] expval);
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//$display("check_s %x\n", i);
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if (i !== expval) $stop;
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endtask
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task check_us(input signed [7:0] i, input [7:0] expval);
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//$display("check_us %x\n", i);
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if (i !== expval) $stop;
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endtask
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always @* begin
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sr = a>>b;
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srs = copy_signed(a)>>>b;
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sl = a<<b;
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sls = a<<<b;
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// verilator lint_off WIDTH
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b_s = b>>>4; // Signed
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b_us = b[4:0]>>>4; // Unsigned, due to extract
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check_s ( 3'b111, 8'h07);
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check_s (3'sb111, 8'hff);
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check_us( 3'b111, 8'h07);
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check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements
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// verilator lint_on WIDTH
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end
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reg signed [32:0] bug349;
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initial
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begin
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end
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integer i;
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initial begin
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if ((-1 >>> 3) != -1) $stop; // Decimals are signed
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// verilator lint_off WIDTH
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if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned
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if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers
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// verilator lint_on WIDTH
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if ( (3'sb000 > 3'sb000)) $stop;
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if (!(3'sb000 > 3'sb111)) $stop;
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if ( (3'sb111 > 3'sb000)) $stop;
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if ( (3'sb000 < 3'sb000)) $stop;
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if ( (3'sb000 < 3'sb111)) $stop;
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if (!(3'sb111 < 3'sb000)) $stop;
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if (!(3'sb000 >= 3'sb000)) $stop;
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if (!(3'sb000 >= 3'sb111)) $stop;
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if ( (3'sb111 >= 3'sb000)) $stop;
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if (!(3'sb000 <= 3'sb000)) $stop;
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if ( (3'sb000 <= 3'sb111)) $stop;
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if (!(3'sb111 <= 3'sb000)) $stop;
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// When we multiply overflow, the sign bit stays correct.
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if ( (4'sd2*4'sd8) != 4'd0) $stop;
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// From the spec:
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// verilator lint_off WIDTH
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i = -12 /3; if (i !== 32'hfffffffc) $stop;
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i = -'d12 /3; if (i !== 32'h55555551) $stop;
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i = -'sd12 /3; if (i !== 32'hfffffffc) $stop;
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i = -4'sd12 /3; if (i !== 32'h00000001) $stop;
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// verilator lint_on WIDTH
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// verilator lint_off WIDTH
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bug349 = 4'sb1111 - 1'b1;
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if (bug349 != 32'he) $stop;
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end
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function signed [15:0] copy_signed;
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input [15:0] ai;
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copy_signed = ai;
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endfunction
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integer cyc; initial cyc = 0;
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wire [31:0] ucyc = cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us);
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`endif
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case (cyc)
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0: begin
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a <= 16'sh8b1b; b <= 5'sh1f; // -1
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end
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1: begin
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// Check spaces in constants
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a <= 16 'sh 8b1b; b <= 5'sh01; // -1
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end
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2: begin
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a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned
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if (ucyc / 1 != 32'd2) $stop;
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if (ucyc / 2 != 32'd1) $stop;
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if (ucyc * 1 != 32'd2) $stop;
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if (ucyc * 2 != 32'd4) $stop;
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if (ucyc * 3 != 32'd6) $stop;
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if (cyc * 32'sd1 != 32'sd2) $stop;
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if (cyc * 32'sd2 != 32'sd4) $stop;
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if (cyc * 32'sd3 != 32'sd6) $stop;
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end
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3: begin
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a <= 16'sh0048; b <= 5'sh1f;
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if (ucyc * 1 != 32'd3) $stop;
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if (ucyc * 2 != 32'd6) $stop;
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if (ucyc * 3 != 32'd9) $stop;
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if (ucyc * 4 != 32'd12) $stop;
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if (cyc * 32'sd1 != 32'sd3) $stop;
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if (cyc * 32'sd2 != 32'sd6) $stop;
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if (cyc * 32'sd3 != 32'sd9) $stop;
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end
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4: begin
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a <= 16'sh4154; b <= 5'sh02;
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end
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5: begin
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a <= 16'shc3e8; b <= 5'sh12;
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end
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6: begin
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a <= 16'sh488b; b <= 5'sh02;
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end
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9: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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case (cyc)
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0: ;
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1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
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2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop;
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3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
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4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop;
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5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop;
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6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
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7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop;
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8: ;
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9: ;
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endcase
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end
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endmodule
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module by_width (
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input clk
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);
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parameter WIDTH=1;
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reg signed i1;
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reg signed [62:0] i63;
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reg signed [64:0] i65;
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// verilator lint_off WIDTH
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wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1;
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wire signed [WIDTH-1:0] i1ext = i1;
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wire signed [WIDTH-1:0] i63ext = i63;
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wire signed [WIDTH-1:0] i65ext = i65;
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// verilator lint_on WIDTH
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integer cyc; initial cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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i1 <= cyc[0];
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i63 <= {63{cyc[0]}};
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i65 <= {65{cyc[0]}};
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case (cyc)
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1: begin
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if (i1extp != {WIDTH{1'b0}}) $stop;
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if (i1ext != {WIDTH{1'b0}}) $stop;
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if (i63ext != {WIDTH{1'b0}}) $stop;
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if (i65ext != {WIDTH{1'b0}}) $stop;
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end
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2: begin
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if (i1extp != {WIDTH{1'b1}}) $stop;
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if (i1ext != {WIDTH{1'b1}}) $stop;
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if (i63ext != {WIDTH{1'b1}}) $stop;
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if (i65ext != {WIDTH{1'b1}}) $stop;
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end
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default: ;
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endcase
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end
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endmodule
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