forked from github/verilator
32 lines
646 B
Systemverilog
32 lines
646 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in
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);
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parameter P32 = 32;
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parameter P24 = 24;
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localparam P29 = P24 + 5;
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input clk;
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output reg [P24-1:0] out;
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input [P29 - 1:0] in;
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always @(posedge clk) begin
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if (P29 >= P24) begin
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out <= in[P29 - 1 -: P24];
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end
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else begin
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out <= {{(P24 - P29){1'b0}}, in};
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end
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end
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endmodule
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