forked from github/verilator
70 lines
1.5 KiB
Systemverilog
70 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Clifford Wolf.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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wire [31:0] y;
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reg a;
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test004 sub (/*AUTOINST*/
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// Outputs
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.y (y[31:0]),
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// Inputs
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.a (a));
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y);
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`endif
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cyc <= cyc + 1;
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if (cyc==0) begin
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a <= 0;
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end
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else if (cyc==1) begin
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a <= 1;
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if (y != 32'h0) $stop;
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end
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else if (cyc==2) begin
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if (y != 32'h010000ff) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module test004(a, y);
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input a;
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output [31:0] y;
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wire [7:0] y0;
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wire [7:0] y1;
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wire [7:0] y2;
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wire [7:0] y3;
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assign y = {y0,y1,y2,y3};
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localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01
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localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00
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localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00
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localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff
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localparam [7:0] zero = 0;
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initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3);
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assign y0 = a ? v0 : zero;
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assign y1 = a ? v1 : zero;
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assign y2 = a ? v2 : zero;
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assign y3 = a ? v3 : zero;
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endmodule
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