forked from github/verilator
26 lines
744 B
Systemverilog
26 lines
744 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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// This isn't a width violation, as +/- 1'b1 is a common idiom
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// that's fairly harmless
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wire [4:0] five = 5'd5;
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wire [4:0] suma = five + 1'b1;
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wire [4:0] sumb = 1'b1 + five;
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wire [4:0] sumc = five - 1'b1;
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wire [4:0] neg5 = - five;
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wire [5:0] neg6 = - five;
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// Relatively harmless < or <= compared with something less wide
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localparam [1:0] THREE = 3;
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int a;
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initial for (a = 0; a < THREE; ++a) $display(a);
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initial for (a = 0; a <= THREE; ++a) $display(a);
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endmodule
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