forked from github/verilator
20 lines
437 B
Systemverilog
20 lines
437 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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config cfgBad;
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design rtlLib.top;
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default liblist rtlLib;
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instance top.a2 liblist gateLib;
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include none;
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library rtlLib *.v;
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include aa;
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use gateLib;
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cell rtlLib.cell;
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endconfig
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module t;
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endmodule
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