forked from github/verilator
21 lines
443 B
Systemverilog
21 lines
443 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off PINNOTFOUND */
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module a;
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localparam A=1;
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generate
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if (A==0)
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begin
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b b_inst1 (.x(1'b0)); // nonexistent port
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b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
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end
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endgenerate
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endmodule
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module b;
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endmodule
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