forked from github/verilator
52 lines
1.5 KiB
Systemverilog
52 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Julien Margetts.
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// SPDX-License-Identifier: Unlicense
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module t (/*AUTOARG*/ out, out2, in );
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input [9:0] in;
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output reg [3:0] out;
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output reg [3:0] out2;
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// Should be no latch here since the input space is fully covered
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always @* begin
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casez (in)
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10'b0000000000 : out = 4'h0;
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10'b?????????1 : out = 4'h0;
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10'b????????10 : out = 4'h1;
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10'b???????100 : out = 4'h2;
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10'b??????1000 : out = 4'h3;
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10'b?????10000 : out = 4'h4;
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10'b????100000 : out = 4'h5;
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10'b???1000000 : out = 4'h6;
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10'b??10000000 : out = 4'h7;
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10'b?100000000 : out = 4'h8;
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10'b1000000000 : out = 4'h9;
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endcase
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end
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// Should detect a latch here since not all paths assign
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// BUT we don't because warnOff(LATCH) is set for any always containing a
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// complex case statement
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always @* begin
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casez (in)
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10'b0000000000 : out2 = 4'h0;
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10'b?????????1 : out2 = 4'h0;
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10'b????????10 : out2 = 4'h1;
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10'b???????100 : out2 = 4'h2;
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10'b??????1000 : out2 = 4'h3;
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10'b?????10000 : /* No assignement */ ;
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10'b????100000 : out2 = 4'h5;
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10'b???1000000 : out2 = 4'h6;
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10'b??10000000 : out2 = 4'h7;
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10'b?100000000 : out2 = 4'h8;
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10'b1000000000 : out2 = 4'h9;
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endcase
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end
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endmodule
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