forked from github/verilator
63 lines
1.3 KiB
Systemverilog
63 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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q,
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// Inputs
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clk, d
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);
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input clk;
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input d;
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output wire [1:0] q;
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// This demonstrates how warning disables should be propagated across module boundaries.
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m1 m1 (/*AUTOINST*/
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// Outputs
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.q (q[1:0]),
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// Inputs
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.clk (clk),
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.d (d));
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endmodule
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module m1
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(
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input clk,
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input d,
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output wire [1:0] q
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);
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m2 m2 (/*AUTOINST*/
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// Outputs
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.q (q[1:0]),
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// Inputs
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.clk (clk),
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.d (d));
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endmodule
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module m2
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(
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input clk,
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input d,
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// Due to bug the below disable used to be ignored.
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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output reg [1:0] q
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// verilator lint_on UNOPT
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// verilator lint_on UNOPTFLAT
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);
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always @* begin
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q[1] = d;
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end
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always @* begin
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q[0] = q[1];
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end
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endmodule
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