forked from github/verilator
15 lines
289 B
Systemverilog
15 lines
289 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2018 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
package defs;
|
|
int sig;
|
|
endpackage
|
|
|
|
import defs::*;
|
|
|
|
module t;
|
|
endmodule
|