forked from github/verilator
68 lines
1.4 KiB
Systemverilog
68 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Josh Redford.
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// SPDX-License-Identifier: CC0-1.0
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interface my_if #( parameter integer DW = 8 ) (input clk);
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localparam DW_LOCAL = DW;
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logic valid;
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logic [DW-1:0] data;
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modport slave_mp (
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input valid,
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input data
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);
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modport master_mp (
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output valid,
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output data
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);
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function automatic integer width();
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return $bits(data);
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endfunction
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generate
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if (DW < 4)
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begin: dw_lt_4_G
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function automatic integer min_width();
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return 4;
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endfunction
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end
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else
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begin: dw_ge_4_G
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function automatic integer min_width();
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return 8;
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endfunction
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end
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endgenerate
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endinterface
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module t
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(
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input wire clk,
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my_if in_if,
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my_if out_if
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);
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assign out_if.valid = in_if.valid;
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assign out_if.data = in_if.data;
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my_if my_i (.clk(clk));
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initial
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begin
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$display(in_if.DW_LOCAL);
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$display(in_if.width());
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$display(in_if.dw_ge_4_G.min_width());
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$display(out_if.DW_LOCAL);
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$display(out_if.width());
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$display(out_if.dw_ge_4_G.min_width());
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end
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endmodule
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