forked from github/verilator
40 lines
842 B
Systemverilog
40 lines
842 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Josh Redford.
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// SPDX-License-Identifier: CC0-1.0
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interface my_if #(
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parameter DW = 8
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) ();
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logic valid;
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logic [DW-1:0] data ;
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modport slave_mp (
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input valid,
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input data
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);
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modport master_mp (
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output valid,
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output data
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);
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endinterface
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module t
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(
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input wire clk,
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my_if.slave_mp in_if [2],
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my_if.master_mp out_if [2]
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);
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assign out_if[0].valid = in_if[0].valid;
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assign out_if[0].data = in_if[0].data;
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assign out_if[1].valid = in_if[1].valid;
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assign out_if[1].data = in_if[1].data;
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endmodule
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