forked from github/verilator
23 lines
486 B
Systemverilog
23 lines
486 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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rbad, rok
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);
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input real rbad;
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input real rok;
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event ebad;
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struct packed { int a; } sok;
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always @ (rok) $stop;
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always @ (sok) $stop;
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always @ (posedge rbad) $stop;
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always @ (posedge ebad) $stop;
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endmodule
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