forked from github/verilator
110 lines
2.9 KiB
Systemverilog
110 lines
2.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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data_out,
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// Inputs
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wr, wa, rst_l, rd, ra, data_in, clk
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);
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input clk;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [31:0] data_in; // To sub of reg_1r1w.v
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input [7:0] ra; // To sub of reg_1r1w.v
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input rd; // To sub of reg_1r1w.v
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input rst_l; // To sub of reg_1r1w.v
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input [7:0] wa; // To sub of reg_1r1w.v
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input wr; // To sub of reg_1r1w.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [31:0] data_out; // From sub of reg_1r1w.v
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// End of automatics
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reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
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sub
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(/*AUTOINST*/
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// Outputs
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.data_out (data_out[31:0]),
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// Inputs
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.data_in (data_in[31:0]),
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.ra (ra[7:0]),
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.wa (wa[7:0]),
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.wr (wr),
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.rd (rd),
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.clk (clk),
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.rst_l (rst_l));
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endmodule
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module reg_1r1w
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#(
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parameter WIDTH=32,
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parameter ADRWID=10,
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parameter DEPTH=1024,
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parameter RST=0
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)
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(/*AUTOARG*/
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// Outputs
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data_out,
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// Inputs
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data_in, ra, wa, wr, rd, clk, rst_l
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);
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input [WIDTH-1:0] data_in;
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input [ADRWID-1:0] ra;
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input [ADRWID-1:0] wa;
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input wr;
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input rd;
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input clk;
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input rst_l;
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output [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] array [DEPTH-1:0];
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reg [ADRWID-1:0] ra_r, wa_r;
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reg [WIDTH-1:0] data_in_r;
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reg wr_r;
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reg rd_r;
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integer x;
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// Message 679
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always @(posedge clk) begin
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int tmp = x + 1;
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if (tmp !== x + 1) $stop;
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end
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always @(posedge clk or negedge rst_l) begin
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if (!rst_l) begin
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for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
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if (RST == 1) begin
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array[x] <= 0;
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end
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end
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ra_r <= 0;
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wa_r <= 0;
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wr_r <= 0;
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rd_r <= 0;
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data_in_r <= 0;
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end
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else begin
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ra_r <= ra;
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wa_r <= wa;
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wr_r <= wr;
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rd_r <= rd;
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data_in_r <= data_in;
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if (wr_r) array[wa_r] <= data_in_r;
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end
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end
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endmodule
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// Local Variables:
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// verilog-auto-inst-param-value: t
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// End:
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