forked from github/verilator
77 lines
1.5 KiB
Systemverilog
77 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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out1, out2, out3, out4, out5, out6, out7, out8,
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// Inputs
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clk, d
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);
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input clk;
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input d;
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output reg out1;
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output reg out2;
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output reg out3;
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output reg out4;
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output reg out5;
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output reg out6;
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output reg out7;
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output reg out8;
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assign out1 = 1'b0;
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always_comb out1 = d; // <--- Warning
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assign out2 = d;
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always_comb out2 = 1'b0; // <--- Warning
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always_comb out3 = d;
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assign out3 = 1'b0; // <--- Warning
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always_comb out4 = 1'b0;
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assign out4 = d; // <--- Warning
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always_comb out5 = 1'b0;
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always_comb out5 = d; // <--- Warning
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always_comb out6 = d;
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always_comb out6 = 1'b0; // <--- Warning
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always_comb begin
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out7 = 1'b0;
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out7 = d;
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end
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always_comb begin
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out8 = d;
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out8 = 1'b0;
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end
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reg [1:0] arr_packed;
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reg arr_unpacked [0:1];
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reg [1:0] gen_arr_packed;
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reg gen_arr_unpacked [0:1];
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genvar g;
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always_comb begin
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arr_packed[0] = d;
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arr_packed[1] = d;
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end
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always_comb begin
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arr_unpacked[0] = d;
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arr_unpacked[1] = d;
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end
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generate
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for (g=0; g<2; ++g) begin
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always_comb gen_arr_packed[g] = d;
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always_comb gen_arr_unpacked[g] = d;
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end
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endgenerate
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endmodule
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