forked from github/verilator
50 lines
920 B
Systemverilog
50 lines
920 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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mid, o3,
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// Inputs
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clk, i3
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);
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input clk;
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output logic mid;
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input i3;
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output logic o3;
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wire [15:0] temp1;
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wire [15:0] temp1_d1r;
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logic setbefore;
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always_comb begin
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setbefore = 1'b1;
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if (setbefore) setbefore = 1'b0; // fine
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end
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always_comb begin
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if (mid)
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temp1 = 'h0;
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else
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temp1 = (temp1_d1r - 'h1);
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mid = (temp1_d1r == 'h0); // BAD
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end
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always_comb begin
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o3 = 'h0;
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case (i3)
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1'b1: begin
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o3 = i3;
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end
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default: ;
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endcase
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end
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always_ff @ (posedge clk) begin
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temp1_d1r <= temp1;
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end
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endmodule
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