forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
111 lines
3.4 KiB
Systemverilog
111 lines
3.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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module secret #(parameter GATED_CLK = 0)
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(
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input [31:0] accum_in,
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output wire [31:0] accum_out,
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input accum_bypass,
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output [31:0] accum_bypass_out,
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input s1_in,
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output logic s1_out,
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input s1up_in[2],
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output logic s1up_out[2],
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input [1:0] s2_in,
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output logic [1:0] s2_out,
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input [7:0] s8_in,
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output logic [7:0] s8_out,
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input [32:0] s33_in,
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output logic [32:0] s33_out,
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input [63:0] s64_in,
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output logic [63:0] s64_out,
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input [64:0] s65_in,
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output logic [64:0] s65_out,
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input [128:0] s129_in,
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output logic [128:0] s129_out,
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input [3:0] [31:0] s4x32_in,
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output logic [3:0] [31:0] s4x32_out,
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/*verilator lint_off LITENDIAN*/
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input [0:15] s6x16up_in[0:1][2:0],
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output logic [0:15] s6x16up_out[0:1][2:0],
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/*verilator lint_on LITENDIAN*/
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input [15:0] s8x16up_in[1:0][0:3],
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output logic [15:0] s8x16up_out[1:0][0:3],
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input [15:0] s8x16up_3d_in[1:0][0:1][0:1],
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output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1],
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input clk_en,
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input clk /*verilator clocker*/);
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logic [31:0] secret_accum_q = 0;
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logic [31:0] secret_value = 7;
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initial $display("created %m");
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logic the_clk;
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generate
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if (GATED_CLK != 0) begin: yes_gated_clock
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logic clk_en_latch;
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/* verilator lint_off COMBDLY */
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/* verilator lint_off LATCH */
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always_comb if (clk == '0) clk_en_latch <= clk_en;
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/* verilator lint_on LATCH */
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/* verilator lint_on COMBDLY */
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assign the_clk = clk & clk_en_latch;
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end else begin: no_gated_clock
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assign the_clk = clk;
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end
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endgenerate
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always @(posedge the_clk) begin
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secret_accum_q <= secret_accum_q + accum_in + secret_value;
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end
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// Test combinatorial paths of different sizes
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always @(*) begin
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s1_out = s1_in;
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s1up_out = s1up_in;
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s2_out = s2_in;
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s8_out = s8_in;
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s64_out = s64_in;
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s65_out = s65_in;
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s129_out = s129_in;
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s4x32_out = s4x32_in;
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end
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for (genvar i = 0; i < 3; ++i) begin
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assign s6x16up_out[0][i] = s6x16up_in[0][i];
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assign s6x16up_out[1][i] = s6x16up_in[1][i];
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end
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for (genvar i = 0; i < 4; ++i) begin
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assign s8x16up_out[0][i] = s8x16up_in[0][i];
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assign s8x16up_out[1][i] = s8x16up_in[1][i];
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end
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for (genvar i = 0; i < 8; ++i) begin
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assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]];
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end
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sub sub (.sub_in(s33_in), .sub_out(s33_out));
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// Test sequential path
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assign accum_out = secret_accum_q;
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// Test mixed combinatorial/sequential path
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assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
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final $display("destroying %m");
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endmodule
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module sub (
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input [32:0] sub_in,
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output [32:0] sub_out);
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/*verilator no_inline_module*/
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assign sub_out = sub_in;
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endmodule
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