forked from github/verilator
50 lines
1.0 KiB
Systemverilog
50 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Arkadiusz Kozdra.
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// SPDX-License-Identifier: CC0-1.0
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// See also t_interface_virtual.v
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interface PBus;
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logic req, grant;
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logic [7:0] addr, data;
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modport phy(input addr, ref data);
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endinterface
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interface QBus;
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endinterface
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typedef virtual PBus vpbus_t;
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module t (/*AUTOARG*/);
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PBus p8;
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QBus q8;
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vpbus_t v8;
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virtual PBus.phy v8_phy;
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logic data;
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initial begin
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v8 = p8;
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p8 = v8; // error
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v8 = q8; // error
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v8_phy = p8;
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v8_phy = v8;
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v8_phy = p8.phy;
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v8 = v8_phy; // error
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v8 = p8.phy; // error
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data = p8.phy; // error
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data = v8_phy; // error
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data = v8; // error
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data = p8; // error
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v8 = data; // error
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v8.grant = 1'b1;
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$display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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