forked from github/verilator
24 lines
573 B
Systemverilog
24 lines
573 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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simple_bus #(.WIDTH(simple.get_width())) sb_intf();
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simple_bus #(.WIDTH(sb_intf.get_width())) simple();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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interface simple_bus #(parameter int WIDTH = 8);
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logic [WIDTH-1:0] data;
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function automatic int get_width();
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return WIDTH;
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endfunction
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endinterface
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