forked from github/verilator
38 lines
824 B
Systemverilog
38 lines
824 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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interface iface(input logic clk);
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logic [31:0] d = 0;
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logic [31:0] q = 0;
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endinterface
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module mod(a);
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iface a; // This is not a CELL, it is a port declaration
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always @(posedge a.clk) a.q <= a.d;
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endmodule
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module t(clk);
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input clk;
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iface iface_inst(clk);
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mod mod_inst(iface_inst);
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int cyc = 0;
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always @(posedge clk) begin
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iface_inst.d <= cyc;
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if (cyc > 1 && iface_inst.q != cyc - 2) $stop;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 100) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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