forked from github/verilator
146 lines
3.2 KiB
Systemverilog
146 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by John Stevenson.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef logic [31:0] unique_id_t;
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typedef struct packed {
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unique_id_t foo;
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} inner_thing_t;
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typedef struct packed {
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inner_thing_t bar;
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inner_thing_t baz;
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} outer_thing_t;
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endpackage
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import pkg::*;
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interface the_intf
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#(parameter M=5);
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outer_thing_t [M-1:0] things;
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logic valid;
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modport i (
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output things,
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output valid);
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modport t (
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input things,
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input valid);
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endinterface
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module ThingMuxOH
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#(
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parameter NTHINGS = 1,
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parameter M = 5 )
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(
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input logic [NTHINGS-1:0] select_oh,
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the_intf.t things_in [NTHINGS-1:0],
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the_intf.i thing_out
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);
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assign thing_out.valid = things_in[0].valid;
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endmodule
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module ThingMuxShort
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#(
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parameter NTHINGS = 1,
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parameter M = 5 )
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(
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input logic [NTHINGS-1:0] select_oh,
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the_intf.t things_in [NTHINGS],
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the_intf.i thing_out
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);
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assign thing_out.valid = things_in[0].valid;
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endmodule
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module Thinker
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#(
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parameter M = 5,
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parameter N = 2)
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(
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input logic clk,
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input logic reset,
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input unique_id_t uids[0:N-1],
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the_intf.t thing_inp,
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the_intf.i thing_out
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);
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the_intf #(.M(M)) curr_things [N-1:0] ();
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the_intf #(.M(M)) prev_things [N-1:0] ();
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the_intf #(.M(M)) s_things [N] ();
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the_intf #(.M(M)) curr_thing ();
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the_intf #(.M(M)) prev_thing ();
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the_intf #(.M(M)) s_thing ();
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logic [N-1:0] select_oh;
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// 1st mux:
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ThingMuxOH #(
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.NTHINGS ( N ),
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.M ( M ))
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curr_thing_mux(
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.select_oh( select_oh ),
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.things_in( curr_things ),
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.thing_out( curr_thing ));
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// 2nd mux, comment this out and no problem:
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ThingMuxOH #(
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.NTHINGS ( N ),
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.M ( M ))
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prev_thing_mux(
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.select_oh( select_oh ),
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.things_in( prev_things ),
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.thing_out( prev_thing ));
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// 3rd mux, using short array nomenclature:
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ThingMuxShort #(
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.NTHINGS ( N ),
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.M ( M ))
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s_thing_mux(
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.select_oh( select_oh ),
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.things_in( s_things ),
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.thing_out( s_thing ));
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endmodule
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module t
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(
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input logic clk,
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input logic reset
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);
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localparam M = 5;
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localparam N = 2;
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unique_id_t uids[0:N-1];
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the_intf #(.M(M)) thing_inp();
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the_intf #(.M(M)) thing_out();
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Thinker #(
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.M ( M ),
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.N ( N ))
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thinker(
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.clk ( clk ),
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.reset ( reset ),
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.uids ( uids ),
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.thing_inp( thing_inp ),
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.thing_out( thing_out ));
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// Previously there was a problem in V3Inst if non-default parameters was used
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localparam K = 2;
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the_intf #(.M(K)) thing_inp2();
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the_intf #(.M(K)) thing_out2();
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Thinker #(
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.M ( K ),
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.N ( N ))
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thinker2(
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.clk ( clk ),
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.reset ( reset ),
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.uids ( uids ),
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.thing_inp( thing_inp2 ),
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.thing_out( thing_out2 ));
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endmodule
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