forked from github/verilator
22 lines
392 B
Systemverilog
22 lines
392 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire foo;
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wire bar;
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sub sub (.*, .*);
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sub sub (foo, .*);
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sub sub (foo, .bar);
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endmodule
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module sub (input foo, input bar);
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endmodule
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