forked from github/verilator
38 lines
636 B
Systemverilog
38 lines
636 B
Systemverilog
// DESCRIPTION::Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct packed {
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logic signed [63:0] b;
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} a_t;
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a_t a_r;
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a_t a_n;
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logic signed [63:0] b;
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logic res;
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assign b = a_r.b;
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always_comb begin
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a_n = a_r;
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res = '0;
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if (b inside {1, 2}) begin
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res = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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a_r <= a_n;
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end
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endmodule
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