forked from github/verilator
47 lines
1023 B
Systemverilog
47 lines
1023 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg _ranit;
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`include "t_initial_inc.vh"
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// surefire lint_off STMINI
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initial assign user_loaded_value = 1;
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initial _ranit = 0;
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always @ (posedge clk) begin
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if (!_ranit) begin
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_ranit <= 1;
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// Test $time
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// surefire lint_off CWECBB
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if ($time<20) $write("time<20\n");
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// surefire lint_on CWECBB
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// Test $write
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$write ("[%0t] %m: User loaded ", $time);
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$display ("%b", user_loaded_value);
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if (user_loaded_value!=1) $stop;
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// Test $c
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`ifdef VERILATOR
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$c ("VL_PRINTF(\"Hi From C++\\n\");");
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`endif
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user_loaded_value <= 2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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