forked from github/verilator
71 lines
1.5 KiB
Systemverilog
71 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class Icempty;
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endclass : Icempty
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interface class Icls1;
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localparam LP1 = 1;
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pure virtual function int icf1;
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pure virtual function int icfboth;
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pure virtual function int icfpartial;
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endclass
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interface class Iext1 extends Icls1;
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pure virtual function int icf101;
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endclass
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interface class Icls2;
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pure virtual function int icf2(int in);
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pure virtual function int icfboth;
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endclass
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virtual class Base implements Iext1, Icls2;
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virtual function int icf1;
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return 1;
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endfunction
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virtual function int icf101;
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return 101;
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endfunction
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virtual function int icf2(int in);
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return in + 2;
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endfunction
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virtual function int icfboth;
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return 3;
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endfunction
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pure virtual function int icfpartial;
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endclass
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class Cls extends Base;
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virtual function int icfpartial;
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return 62;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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Cls c;
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Iext1 i1;
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initial begin
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if (Icls1::LP1 != 1) $stop;
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c = new;
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if (c.icf1() != 1) $stop;
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if (c.icf101() != 101) $stop;
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if (c.icf2(1000) != 1002) $stop;
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if (c.icfpartial() != 62) $stop;
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i1 = c;
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if (i1.icf1() != 1) $stop;
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if (i1.icf101() != 101) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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