forked from github/verilator
49 lines
977 B
Systemverilog
49 lines
977 B
Systemverilog
// DESCRIPTION: Verilator: Test for issue #2267
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by James Pallister.
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// SPDX-License-Identifier: CC0-1.0
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module mod_a;
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mod_inner u_inner;
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mod_a_mon u_a_mon;
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initial begin
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bit x;
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u_inner.x = 1;
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u_a_mon.y = 0;
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u_a_mon.accessor;
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if (u_a_mon.y != 1) begin
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$write("%%Error: Incorrect value placed in submodule\n");
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$stop;
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end
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u_inner.x = 0;
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u_a_mon.accessor;
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if (u_a_mon.y != 0) begin
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$write("%%Error: Incorrect value placed in submodule\n");
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : mod_a
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module mod_inner;
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logic x;
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endmodule : mod_inner
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module mod_a_mon;
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bit y;
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function automatic void accessor;
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begin : accessor_block
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bit read_x = mod_a.u_inner.x;
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y = read_x;
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end
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endfunction
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endmodule
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