forked from github/verilator
48 lines
1.0 KiB
Systemverilog
48 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: Unlicense
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`define HIER_BLOCK /*verilator hier_block*/
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interface byte_ifs(input clk);
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logic [7:0] data;
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modport sender(input clk, output data);
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modport receiver(input clk, input data);
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endinterface;
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module t (/*AUTOARG*/
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// Inputs
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clk
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); `HIER_BLOCK // Top module can not be a hierarchy block
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input wire clk;
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wire [7:0] out0;
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int count = 0;
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byte_ifs in_ifs(.clk(clk));
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byte_ifs out_ifs(.clk(clk));
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assign in_ifs.data = out0;
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sub0 i_sub0(.clk(clk), .in(count), .out(out0));
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sub1 i_sub1(.in(in_ifs), .out(out_ifs));
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endmodule
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module sub0 (
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input wire clk,
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input wire [7:0] in,
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output wire [7:0] out); `HIER_BLOCK
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logic [7:0] ff;
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always_ff @(posedge clk) ff <= in;
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assign out = ff;
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endmodule
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module sub1 (byte_ifs.receiver in, byte_ifs.sender out); `HIER_BLOCK
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assign out.data = in.data;
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endmodule
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