forked from github/verilator
65 lines
1.3 KiB
Systemverilog
65 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish;
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// on success, or $stop.
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//
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// The code as shown applies a random vector to the Test
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// module, then calculates a CRC on the Test module's outputs.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by ____YOUR_NAME_HERE____.
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// SPDX-License-Identifier: CC0-1.0
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module t #
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(
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parameter PIPE = 4
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)(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// These are ok
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sub #(
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.P_STOP (1)
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) u_sub1 ();
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sub #(
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.P_STOP (0)
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) u_sub0 ();
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genvar i;
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for (i = -1; i < 1; i++) begin: SUB_PIPE
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sub #(
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.P_STOP (i)
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) u_sub ();
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end
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub #
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(
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parameter P_START = 1,
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parameter P_STOP = 0
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)(
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);
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initial begin
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for (int i = P_START; i >= P_STOP; --i) begin
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$display("%m %0d..%0d i=%0d", P_START, P_STOP, i);
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end
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end
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endmodule
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