forked from github/verilator
81 lines
2.1 KiB
Systemverilog
81 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire RBL2; // From t of Test.v
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// End of automatics
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wire RWL1 = crc[2];
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wire RWL2 = crc[3];
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Test t (/*AUTOINST*/
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// Outputs
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.RBL2 (RBL2),
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// Inputs
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.RWL1 (RWL1),
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.RWL2 (RWL2));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {63'h0, RBL2};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hb6d6b86aa20a882a
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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output RBL2,
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input RWL1, RWL2);
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// verilator lint_off IMPLICIT
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not I1 (RWL2_n, RWL2);
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bufif1 I2 (RBL2, n3, 1'b1);
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Mxor I3 (n3, RWL1, RWL2_n);
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// verilator lint_on IMPLICIT
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endmodule
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module Mxor (output out, input a, b);
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assign out = (a ^ b);
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endmodule
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