forked from github/verilator
34 lines
679 B
Systemverilog
34 lines
679 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Thomas Dzetkulic.
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// SPDX-License-Identifier: CC0-1.0
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module fnor2(f, a, b);
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parameter W = 1;
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output [W-1:0]f;
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input [W-1:0] a, b;
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supply0 gnd;
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supply1 vcc;
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generate
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genvar i;
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for (i = 0; i < W; i = i + 1) begin
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wire w;
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pmos(f[i], w, a[i]);
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pmos(w, vcc, b[i]);
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nmos(f[i], gnd, a[i]);
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nmos(f[i], gnd, b[i]);
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end
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endgenerate
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endmodule
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module t(f, a, b);
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output [1:0] f;
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input [1:0] a, b;
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fnor2 #(2) n(f, a, b);
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endmodule
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