forked from github/verilator
30 lines
469 B
Systemverilog
30 lines
469 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug1588
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interface intf;
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logic a;
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modport source(output a);
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endinterface
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module m1
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(
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input logic value,
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intf.source b
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);
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endmodule
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module t;
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intf ifs;
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m1 m0(
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j.e(0),
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.b(ifs)
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);
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genvar j;
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endmodule
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