forked from github/verilator
51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug591
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module t (/*AUTOARG*/);
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function real ABS (real num);
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ABS = (num < 0) ? -num : num;
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endfunction
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function logic range_chk;
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input real last;
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input real period;
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input real cmp;
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range_chk = 0;
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if ( last >= 0 ) begin
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if ( ABS(last - period) > cmp ) begin
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range_chk = 1;
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end
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end
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endfunction
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function integer ceil;
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input num;
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real num;
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if (num > $rtoi(num))
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ceil = $rtoi(num) + 1;
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else
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// verilator lint_off REALCVT
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ceil = num;
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// verilator lint_on REALCVT
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endfunction
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initial begin
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if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop;
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if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop;
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if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop;
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if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop;
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if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop;
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if (ceil(-2.1) != -2) $stop;
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if (ceil(2.1) != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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