forked from github/verilator
57 lines
1.4 KiB
Systemverilog
57 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003-2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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integer cyc; initial cyc=1;
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integer sum;
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integer cpre;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cpre = cyc;
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cyc <= cyc + 1;
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if (cyc==1) begin
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if (mlog2(32'd0) != 32'd0) $stop;
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if (mlog2(32'd1) != 32'd0) $stop;
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if (mlog2(32'd3) != 32'd2) $stop;
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sum <= 32'd0;
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end
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else if (cyc<90) begin
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// (cyc) so if we trash the variable things will get upset.
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sum <= mlog2(cyc) + sum * 32'd42;
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if (cpre != cyc) $stop;
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end
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else if (cyc==90) begin
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if (sum !== 32'h0f12bb51) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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function integer mlog2;
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input [31:0] value;
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integer i;
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begin
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if(value < 32'd1) begin
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mlog2 = 0;
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end
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else begin
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value = value - 32'd1;
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mlog2 = 0;
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for(i=0;i<32;i=i+1) begin
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if(value > 32'd0) begin
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mlog2 = mlog2 + 1;
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end
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value = value >> 1;
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end
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end
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end
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endfunction
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endmodule
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