forked from github/verilator
55 lines
1.0 KiB
Systemverilog
55 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module Test(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in
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);
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// Replace this module with the device under test.
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//
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// Change the code in the t module to apply values to the inputs and
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// merge the output values into the result vector.
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input clk;
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input [31:0] in;
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output reg [31:0] out;
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integer cyc = 0;
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SubTest subtest(.out);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d\n", $time, cyc);
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`endif
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cyc <= cyc + 1;
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if (cyc < 99) begin
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subtest.block.set(in);
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end
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else begin
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$write("[%0t] cyc==%0d\n", $time, cyc);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module SubTest(
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output logic[31:0] out
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);
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if (1) begin : block
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function void set(logic[31:0] in);
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out <= in;
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endfunction
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end : block
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endmodule
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