forked from github/verilator
102 lines
2.2 KiB
Systemverilog
102 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define zednkw 200
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module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
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input zfghtn;
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input [4:0] cjtmau;
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input vipmpg;
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input [7:0] knquim;
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input [7:0] kqxkkr;
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reg covfok;
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reg [15:0] xwieqw;
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reg [2:0] ofnjjt;
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reg [37:0] hdsejo[1:0];
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reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
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reg vrqrih, ryyjxy;
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reg fgzsox;
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wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
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wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
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wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
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wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
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wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
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wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
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wire smxixw = vrqrih | (ryyjxy & ktsveg);
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wire [7:0] grvsrs, kyxrft, uxhkka;
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wire [7:0] eianuv = 8'h01 << ofnjjt;
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wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
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wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
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wire [7:0] nahzat = {8{iytyol}} & eianuv;
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genvar i;
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generate
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for (i=0;i<8;i=i+1)
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begin : dnlpyw
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DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
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knquim[3:0], covfok, grvsrs[i]);
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DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
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knquim[7:4], covfok, kyxrft[i]);
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DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
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kqxkkr[3:0], covfok, uxhkka[i]);
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end
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endgenerate
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endmodule
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module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
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input clk, fgzsox, fckiyr, covfok;
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input [3:0] uezcjy;
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output juvlsh;
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task Xinit;
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begin
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`ifdef TEST_HARNESS
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khgawe = 1'b0;
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`endif
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end
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endtask
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function X;
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input vrdejo;
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begin
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`ifdef TEST_HARNESS
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if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
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`endif
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X = vrdejo;
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end
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endfunction
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task Xcheck;
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input vzpwwy;
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begin
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end
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endtask
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reg [3:0] udbvtl;
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assign juvlsh = |udbvtl;
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wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
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wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
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always @(posedge clk)
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begin
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Xinit;
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if (X(qqibou))
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udbvtl <= #`zednkw mppedc;
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Xcheck(fgzsox);
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end
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endmodule
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