forked from github/verilator
8624ce6a84
* Tests: Add more case that does not match native C++ width (8, 16, 32 or 64). * Use AstVarRef::same() instead of AstNode::sameGateTree() because the latter checks dtype in addition to scope. AstVarRef may have different minWidth in some cases, but the difference should be ignored in the context of bitOpTree optimization.
27 lines
767 B
Perl
Executable File
27 lines
767 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["--compiler msvc", "--stats"], # We have deep expressions we want to test
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);
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execute(
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check_finished => 1,
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);
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if ($Self->{vlt}) {
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file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 3888);
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}
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ok(1);
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1;
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